Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device using a spacer patterning technique.
Due to a limitation in the resolution of an exposure equipment, semiconductor devices of a scale lower than 40 nm are fabricated through a Mesh Spacer Patterning Technology (MSPT) process where a spacer patterning technology (SPT) is performed twice for fine patterning. The MSPT process, however, may include many procedural steps, and requires high fabrication costs and high procedural difficulty due to asymmetricity between a primary SPT process and a secondary SPT process.
To improve the MSPT process, a pillar-type Pillar SPT (PSPT) method has been suggested. According to the PSPT method, spacers are formed after a pillar-type photoresist (PR) mask is formed, and then a spacer at a position where four spacers meet may be used as a hole pattern. The PSPT process reduces not only the number of the procedural steps by more than 10 but also decreases the fabrication costs and the procedural difficulty, compared with the MSPT process.
However, it may be difficult to apply the PSPT process because pillar pattern should be formed using a photoresist mask and the photoresist mask may have small exposure margins, compared with hole pattern.